Rambus to Design Silicon-Proven Memory and Interface Blocks for 14nm-XM FinFET Tech[02/07/2013 11:41 PM]
GlobalFoundries and Rambus this week unveiled plans to collaborate for the development of a broad portfolio of complex semiconductor intellectual property (IP) optimized for GlobalFoundries’ 14nm-XM process tech. Rambus will design standard silicon-proven IP blocks that address the growing needs in applications ranging from high-performance computing to smart mobile devices.
“This extension of our partnership with Rambus will give customers a faster path to take advantage of Rambus’ advanced interface solutions on our new 14nm-XM technology, opening up new avenues for chip designers to innovate on our process technology,” said Mike Noonen, executive vice president of marketing, sales, design and quality at GlobalFoundries.
Rambus will develop a range of high-speed memory and chip-to-chip serial link interfaces optimized for GlobalFoundries processes, including the new 14nm-XM technology, which is the industry’s first 14nm offering based on a modular FinFET technology architecture. This new work will build on past collaboration on several 28nm test chips that demonstrate the capabilities of Rambus’ interfaces for both mobile and server-based applications.
“By engaging early with GlobalFoundries on their advanced 14nm process, we can combine our high speed, mixed signal design expertise with FinFET technology, enabling a broad portfolio of silicon-proven complex IP blocks in advance of customer needs,” said Kevin Donnelly, senior vice president and general manager of the memory and interfaces division at Rambus.
GlobalFoundries’ 14nm-XM offering is based on a modular technology architecture that uses a 14nm FinFET device combined with 20nm-LPM process back-end-of-line (BEOL) interconnect flow, which is well on its way to production. Technology development is already underway, with test silicon running through GlobalFoundries’ Fab 8 in Saratoga County, N.Y. The XM stands for “eXtreme Mobility,” and it is the industry’s leading non-planar architecture that is truly optimized for mobile system-on-chip (SoC) designs, providing a whole product solution from the transistor all the way up to the system level. The technology is expected to deliver a 40%-60% improvement in battery life when compared to today’s two-dimensional planar transistors at the 20nm node.
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