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Toshiba Corp. this week announced the development of an innovative low-power technology for embedded SRAM for application in smartphones and other mobile products. The technology can reduce power consumption of caches inside microprocessors by 27% - 85%.

The new technology reduces active and standby power in temperatures ranging from room temperature (RT) to high temperature (HT) by using a bit line power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A prototype has been confirmed to reduce active and standby power consumption at 25°C by 27% and 85%, respectively.

Longer battery life requires lower power consumption in both high performance and low performance modes (MP3 decoding, background processing). As low performance applications require only tens of MHz operation, SRAM temperature remains around RT, where active and leakage power consumptions are comparable. Given this, the key issue is to reduce active and standby power from HT to RT.

Toshiba's new technology applies a BLPC and DCRC. The BLPC predicts power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It minimizes the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits. The DCRC greatly decreases standby power in the retention circuit by periodically activating itself to update the size of the buffer of the retention driver.

Toshiba will continue to develop technologies that contribute to high performance, low power system LSI for mobile products.

Tags: Toshiba, SRAM, Semiconductor

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