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Taiwan Semiconductor Manufacturing Co. claims that the Moore’s law will survive in the long-term, despite of all issues and lack of its economic feasibility for many chip designers. However, future chips will not only gain logic transistors to drive performance up, but will absorb a lot of untraditional (by today’s standards) functionality.

“If anybody pushes Moore's Law to extremes, TSMC will be there too, but that is not all we do. We also have specialized technologies such as embedded flash, high-voltage, power transistors, MEMS and image sensors – a spectrum of technologies. And as we move monolithic CMOS on to more advanced nodes, all these other technologies cannot be moved along with it – that's where our interposers and 3D technologies will enable system integration that allows them all to be used together in what we call a system super-chip packages,” said Jack Sun, chief technology officer and vice president of R&D at TSMC, in an interview with EETimes web-site.

Traditionally, both vertically integrated makers of semiconductors as well as contract makers of semiconductors, introduced new process technologies every 18 to 24 months. In the recent years the cadence changed a bit since development of new manufacturing processes and building new fabs became extremely expensive; Intel Corp. keeps introducing new fabrication processes every two years and new product families every year proving the financial viability of Moore's law. The world's biggest chipmaker believes that the new process technologies enable it to integrate more functionality into chips while keeping their prices relatively flat.

However, Intel is among a few companies who produce so large amounts of chips that it can cover development costs. For many companies every transition to a new node costs tens, if not hundreds, millions of dollars. As a result, the difference between actual manufacturing costs becomes less important for many chips. Therefore, many companies, including major customers of AMD, believe that they should closely balance the transistor density of its chips so that to maximize economic effects of new manufacturing technologies. Essentially, this results into longer life-cycle of every process technology.

TSMC believes that its interposers and 3D stacking will enable new breed of super chips with functionality beyond what is possible today.

"We have three basic focuses: the first is to continue to push monolithically in CMOS to get the most energy efficient transistors -- providing the largest number of transistors running at the lowest power. We consider CMOS to be like the brain of a system. Secondly we provide specialty technologies that are like your eyes and ears and that are analog and mixed signal. Then thirdly, we provide 3-D technologies with TSVs [through silicon vias], interposers and other wafer-level package capabilities, which allows us to integrate the most advanced logic chips with our specialty technologies. Of course, some customers just want SoCs – and that is fine – but others will want to take advantage of our ability to use 3-D integration to make the whole system smaller using system-scaling and system integration – what we call system super-chips," said Mr. Sun.

Tags: TSMC, Semiconductor, 300mm, 450mm, Business, 28nm, 20nm, Moore's Law, Intel, ARM, Globalfoundries


Comments currently: 3
Discussion started: 05/16/13 06:06:21 AM
Latest comment: 05/16/13 12:22:24 PM
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Well technically Moore's Law won't continue but what TSMC means is that as they all run out of the ability to reduce trace size they will add more whistles and bells to convince people they need a newer chippie or electronic toy. Even with stacked transistors there are limits due to cooling challenges.
0 0 [Posted by: beenthere  | Date: 05/16/13 06:06:21 AM]
- collapse thread

I think it's more of a limit of competition. We've hit many barriers to transistor count before, the only difference this time is that intel isn't being challenged.
0 0 [Posted by: evernessince  | Date: 05/16/13 12:22:24 PM]

Regarding heat removal from stacks, that's getting figured out by folks like IBM, Georgia Tech, others. I expect we'll see an additional layer as needed in the stack with TSVs passing vertically and microfluidic heatpipes/channels passing horizontally. Will that add cost? Sure, until high volumes bring the techniques' cost down. But these stacks will become more prevalent since they will allow system bandwidth to keep pace with demand while keeping the I/O power requirements down.
0 0 [Posted by: markwrob  | Date: 05/16/13 10:52:49 AM]


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