Taiwan Semiconductor Manufacturing Co. has released three silicon-validated reference flows within the open innovation platform (OIP) that enable 16 FinFET systems-on-chip (SoC) designs and 3D chip stacking packages. Leading electronic design automation (EDA) vendors collaborated with TSMC to develop and validate all these flows through multiple silicon test vehicles. There are three reference flows.
“These reference flows give designers immediate access to TSMC’s 16FinFET technology and pave the way to 3D IC Through-Transistor-Stacking (TTS) technology. Delivering our most advanced silicon and manufacturing technologies as early and completely as possible to our customers is a major milestone for TSMC and its OIP design ecosystem partners,” said Cliff Hou, vice president of R&D at TSMC.
16FinFET Digital Reference Flow
The 16FinFET digital reference flow uses the ARM Cortex-A15 multicore processor as a validation vehicle for certification. It helps designers adopt the new technology by addressing FinFET structure related challenges of complex 3D resistance capacitance (RC) modeling and quantized device width. In addition, the flow provides methodologies for boosting power, performance and area (PPA) in 16nm, including low-voltage operation analysis, high-resistance layer routing optimization for interconnect resistance minimization, path-based analysis and graph-dased analysis correlation to improve timing closure in automatic place and route (APR).
16FinFET Custom Design Reference Flow
The 16FinFET custom design reference flow enables custom design by addressing the growing complexity of 16FinFET process effects and provides methodologies for design compliance in 16nm manufacturing and reliability.
3D IC Reference Flow
The 3D IC process produces significant silicon scaling, power and performance benefits by integrating multiple components on a single device. TSMC’s 3D IC reference flow addresses emerging integration challenges through 3D stacking. Key features include through-transistor-stacking (TTS) technology; through silicon via (TSV)/microbump and back-side metal routing; TSV-to-TSV coupling extraction.