There is still quite a lot of time left before the new AMD CPUs are out, however, the stir around them keeps boiling. One of the most actively discussed peculiarities of these CPUs remains the integrated on-die memory controller. Of course, the advantages of this solution are undeniable, but we shouldn’t also disregard the limitations this solution imposes, which tells on the supported RAM types in the first place. According to AMD guys who preferred to remain unknown, as we read over here, the issue connected with the support of the new memory types can be solved absolutely trivially: the integrated memory controller can be disabled and its functions will go over to a classical memory controller implemented in the chipset North Bridge.

This way, the final decision is to be made by the platform developers, because once they make up their mind to allow using memory type other than PC2700, they will simply have to develop an efficient memory controller to be integrated into their chipsets.

I would also like to point out that in case of an “external” memory controller, the system memory latency will grow up. The pleasing thing about it is the fact that the adoption of the new RAM types via the external memory controller will not be limited by the bandwidth of the bus between the chipset and the CPU: the major HyperTransport channel between the chipset North Bridge and the CPU boasts linear bandwidth of 3.2GB/sec (each way).

It is also worth mentioning that disabling the controller will either become a temporary or a niche solution. For instance, they will be able to get most efficiency from the memory controller disabling some time closer to the end of 2003, when DDR-II SDRAM becomes mass and AMD will not be ready to introduce a corresponding K8 product. Also the possibility to disable internal systems responsible for the data exchange with RAM may be very useful for multi-processor servers (8, 16, 32 CPUs), where the advantages of the integrated memory controller may be ruined by the delays occurring when the memory within the competence of "remote" CPUs is accessed.