We came across a very interesting rumor from Taiwan over at Digitimes. According to this rumor, AMD is considering the possibility to modify the design of its upcoming 64bit Hammer (K8) chips, and to be more exact to modify the integrated memory controller, which might acquire the support of the new DDR II memory standard (currently it supports only DDR333). Maybe it will also get dual-channel memory support as well. They explain this decision with the fact that K8 CPU are expected to start spreading worldwide only in 2003 (because of some problems with 0.13micron SOI process), and by that time DDR II is expected to arrive to the market. They also claim that this modification will affect the launching schedule for the Hammer processors and they will be postponed from October until December 2002.

To tell the truth, these rumors sound a little bit strange to us. First of all, it is very risky to start redesigning the chip, even slightly, half a year before its mass production, especially since the problems with the manufacturing technology do exist (the current Hammer samples work only at 800MHz instead of the desired 2GHz). And it would be especially risky to start making some major changes in the design, such as introducing the second memory channel.

However, all these rumors are not ungrounded and demonstrate the main bottleneck of hammer CPUs: poor scalability in terms of memory support caused by the integrated controller. Honestly, I didn’t like the idea from the very beginning, although AMD engineers know what they are doing, I suppose. As for the into about the delayed launching, you can simply disregard this info, because both months, October and December belong to Q4 when AMD was actually planning to release its 64bit desktop ClawHammer CPUs.

By the way, if they still redesign the chip, all the chipset makers will have to modify their solutions for K8 CPU. These will be not very big changes, of course, however, I doubt that the chipset manufacturers will like the idea. However, commenting on these rumors the officials from ALi, SiS and VIA claimed that even despite the possible memory controller redesign their chipsets will nevertheless be ready by the end of Q3 2002.

K.J. Chou, general manager of AMD Taiwan, said that so far they have not received notice from headquarters about the schedule or specification changes and they are still planning to introduce the new K8-based Athlon in the fourth quarter, with the workstation/server-use Opteron following later. Of course we have more credibility with the AMD representative rather than rumors, however, we all know very well that even company officials can sometimes conceal the actual intentions of their company :)