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Post to SlashdotIt was reported at Anandtech, that afterwards, Intel is planning to switch to the production of chipsets working with one-channel and dual-channel DDR memory.
According to Intel representatives reports, the company will release several chipsets with dual-channel DDR SDRAM support, right after the autumn release of i845GE and i845PE – upgraded versions of the current DDR SDRAM Intel chipsets with DDR333 memory support.
At the moment, only two chipsets support dual-channel DDR SDRAM – server Intel E7500 and NVIDIA nForce, oriented to AMD processors use. Dual-channel DDR chipsets for Pentium 4 from VIA and SiS will appear later this year. Intel is planning to release the same products only in the second half of 2003, and will be aimed to the use with Pentuium 4, made with 0.09 micron Prescott core.
It is expected that two products will be offered – high-end Granite Bay chipset and Springdale mainstream chipset. Both products will have a dual-channel DDR SDRAM memory controller with DDR333 memory support. Subsequently, the memory subsystems bandwidth in these chipsets will reach 5.3 Gb/sec. This value equals the bandwidth of a future Pentium 4 with a Prescott core, which will work with a 667 MHz Quad Pumped Bus.
Among other interesting features of the future Intel chipsets is the fact that they will go together with a new ICH5 Bridge. Serial ATA and wireless network support, made with 802.11b standard, can be called the main advantage of this chipset. Hub Link 2.0 bus with a 1 Gb/sec bandwidth will connect ICH5 with the North Bridge.
Also, Intel has decided to take out the traditional network controller from the South Bridge into a separate board. The North Bridge will have an additional port, making possible the connection of Fast Ethernet controllers. The bandwidth of this port will be 2 Gb/sec.
That’s the way Intel sees the future of its platforms. I’d like to remind that AMD is promoting a different ideology, based on using HyperTransport and a memory controller embedded in the processor, which allows both a higher bandwidth of the bus between the components of the platform and smaller delays during çàïðîñû to the memory. Soon we will be able to find out, whose approach turned out to be more viable. Don’t forget to visit our web-site in 2003.
