Kingston's EPOC technology mounts DRAM chips in different packages into two overlapping rows on the printed circuit board. The top tier is a row of raised Thin-Small Outline Package (TSOP) memory chips, and the lower tier is a row of smaller Chip Scale Package (CSP) memory chips. There are no chip-level interconnects or physical contact between the two overlapping rows.
Kingston has shipped nearly 10 000 PC133 EPOC modules and to date has not encountered any compatibility issues. This supports the extensive testing conducted by Kingston engineers to ensure that the EPOC technology is robust and reliable, according to Kingston.
Kingston engineers established and met their three objectives for the development of EPOC memory modules. The first objective was to eliminate the long lead-times required to stack memory chips when using third-party stacking companies. Second, Kingston engineers set a design objective requiring the new technology to be as easy to manufacture as standard modules. Finally, the last objective was to enhance thermal performance and overall reliability.
Although there is nothing new in the method of placing the chips one above another, Kingston decided to patent it earlier this year (see this news-story to see our concerns about this and similar facts).
Kingston does not indicate the price of their new memory module and also declines to say when the products will be available.





