All the developers of core-logic sets have introduced their own interconnection protocols between North and South Bridges of the core-logic since the year 1998 because PCI became insufficient in providing enough bandwidth for the current needs while HyperTransport and PCI Express (3GIO) platforms will not be available for a while. Intel brought its Intel Hub Architecture in late 1998, VIA Technologies introduced its V-Link, SiS launched its MuTIOL bus and HyperTransport Consortium headed by AMD offered its HyperTransport Bus. All the transfer protocols were eventually implemented in the actual devices offering wide-bandwidth and high-performance solutions.

Intel Hub Architecture, as well as MuTIOL and V-Link are temporary solutions before Intel and AMD finally unveil their PCI Express (3GIO) and HyperTransport based platforms. Since both of the protocols are universal, it is very interesting to know who of the chipset developers choose HyperTransport and who decides to go with PCI Express.

It is clear that Intel will never use HyperTransport technology and will be fully committed to PCI Express. On the other hand NVIDIA and ALi seem to be very loyal to HyperTransport, for instance, ALi even utilizes it in their Intel Pentium 4 intended chipsets. ATI wants to go with their A-Link and eventually A-Link/2 solutions for their future chipsets and VIA is still considering whether to continue using V-Link, or to go with either Intel or AMD. Although SiS also currently utilises their own MuTIOL, they decided to implement PCI Express interconnection next year. The first I/O bridge that will support the new protocol is the SiS965, offering 8xUSB 2.0, 3xFireWire, LAN, WLAN (!), ATA-33/66/100/133 and Serial ATA-150 support. The newcomer will be available by the end of Summer 2003. Intel itself plans to start using PCI Express as interconnection between North and South Bridges sometimes in April or May 2004 (see this news-story).