AMD Details Its Triple-Gate Transistors

Claims They Will Go Mass in 2007

by Anton Shilov
09/18/2003 | 02:04 PM

At the International Conference on Solid State Devices and Materials in Tokyo, AMD researchers detailed their creation of new triple-gate transistors using next-generation silicon-on-insulator (SOI) and advanced metal gate technologies.

 

The research presented today maximizes transistor switching performance and decreases power-wasting leakage by combining several highly advanced technologies into a single structure.

A unique ultra-thin electrical path using fully depleted silicon-on-insulator (FDSOI) technology is surrounded on three sides with nickel-silicide metal gates. This combination of FDSOI and nickel-silicide metal gates has the effect of straining the silicon lattice within the electrical path to enhance carrier mobility.

Furthermore, the multi-gate, FDSOI structure increases the effective width of the electrical path in the transistor and also provides better electrical control of this path. These factors combine to provide higher “on” current, lower “off” current and faster switching, thereby increasing the overall transistor performance.

AMD’s design delivers up to 50% better performance than any previously published multi-gate research. This surpasses 2009 requirements set by the International Technology Roadmap for Semiconductors (ITRS), but because the design is also highly compatible with current manufacturing techniques, AMD views this technology as a leading candidate for volume production as early as 2007.