TSMC Readies New 90nm Process Technology

by Anton Shilov
10/06/2005 | 08:24 PM

Taiwan Semiconductor Manufacturing Company (TSMC) announced that it had successfully qualified 90nm X Architecture design rules that can enable lower cost, higher performance and lower power designs. TSMC and Cadence Design Systems, who leads X initiative, have collaborated to validate the Cadence X Architecture design solution for the process. The two companies are now engaging mutual customers.

The X Architecture is a new approach to chip design whereby diagonal interconnects are employed to reduce chip costs, increase performance and lower power consumption. Targeted at chips with five or more metal layers, the X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees in relation to conventional orthogonal, or “Manhattan”, architecture. Layers one through three remain unchanged, preserving the design community’s investment in existing cell libraries, memory cells, memory compilers, datapath compilers, and IP hard cores. In addition, the X Architecture allows 45 degrees “wrong-way jogs”, which provides an additional four degrees of freedom in each layer of routing.

The X Architecture’s pervasive use of diagonal routing reduces wirelength by up to 20% and the via count by up to 30%, resulting in significant improvements in chip area, speed, power, and cost. In addition, the X Architecture’s wirelength reduction makes the routing problem 20% easier to solve, resulting in faster timing closure, improved reliability, and a reduction in signal-integrity problems, Cadence claims.

Earlier this year, ATI Technologies, Cadence and TSMC successfully produced the foundry industry’s first X Architecture device – high-performance, high-volume PCI-Express graphics processor designed for desktop and notebook computers”. The ATI device was implemented using the Cadence X Architecture design solution and manufactured using TSMC’s 0.11-micron process. This implementation eliminated one metal layer from the original Manhattan design, reducing die costs. ATI did not reveal which graphics processor was made, but said the new device was expected to enter volume production late in the year.

Cadence X Architecture design solutions for TSMC’s 0.13 micron, 0.11 micron, and 90nm processes are now available to customers. Currently it is unknown who of TSMC customers is likely to utilize the new 90nm process technology.