PCI Express 2.0 Specification Nears Final

PCI Express 2.0 Spec Almost Ready

by Anton Shilov
10/09/2006 | 11:49 PM

PCI-Special Interest Group (PCI-SIG) responsible for development of PCI and PCI Express specifications has announced that it had made the release candidate (revision 0.9) of its PCI Express Base 2.0 specification available for review by member companies.

 

The PCI Express 2.0 specification extends the data rate of PCI Express to 5GT/s (5GHz) in a manner compatible with the existing PCI Express 1.1 specifications that support 2.5GT/s (2.5GHz) signaling. There are a number of improvements made to the protocol and software layers of the architecture – a product of more than three years of design experience by the PCI-SIG members.

Continuing ongoing specification development, PCI-SIG working groups are completing the suite of specifications to enable I/O device virtualization and sharing. The draft Address Translation Services (ATS) 0.9 specification has been released for member review. The Single-Root and Multi-Root device sharing specifications are in various stages of development and will be released to members for review in the near future.

In addition, the PCI Express Cable specification has been released to members at revision 0.9 for 60-day review. The new specification supports cables up to 10 meters in length running at 2.5Gb/s. Cable assemblies have already been measured and validated by the workgroups. The specification will primarily be implemented in disaggregated I/O and backplane usage models. PCI-SIG has decoupled this specification from the PCI Express 2.0 specification (5.0GT/s) and anticipates the final version of the cable specification to be ready by year-end 2006.

With work on PCI Express 2.0 specification nearly complete, PCI-SIG assigned its technical workgroups to investigate and develop the scope for potential extensions of the PCI Express protocols to meet future requirements, such as improved dynamic power controls, optimized synchronization, coherency hints, and more efficient transaction ordering.

These enhancements will be evaluated for possible inclusion in a collection of incremental extensions to the PCI Express architecture intended to improve the range of design options available to emerging markets and computing models. The affected technical workgroups have issued a call for new membership and will study future extensions such as, but not limited to, those within the recent Geneseo proposal from PCI-SIG member companies. These technical workgroups, which are open to all members of the organization, will solicit input from other member companies and recommend future directions to enhance the PCI Express protocols.