by Anton Shilov
03/28/2007 | 08:08 AM
Taiwan Semiconductor Manufacturing Company, the world’s No. 1 contract semiconductor manufacturer, has announced 55nm process technology, an optical shrink for its 65nm fabrication process, which allows to make chips smaller and more energy efficient and does not require designers of processors to fully redevelop their products.
<%BANNER[article]%>“TSMC’s half-node process, including 55nm, is the quickest and simplest way for our customers to be cost competitive in the rapidly changing marketplace. TSMC continues to combine manufacturing superiority with a comprehensive design ecosystem to support customers of any size, from startups to multinational giants,” said Jason Chen, vice president of corporate development of TSMC.
TSMC’s 55nm process technology is a 90% linear-shrink process from 65nm including I/O and analog circuits. The process delivers reportedly significant die cost savings from 65nm, while offering the same speed and 10 to 20% lower power consumption. Because the 55nm process is a direct shrink, chip designers can leverage existing libraries and port their 65nm designs with minimal risk and effort. The 55nm logic family includes general purpose (GP) and consumer (GC) platforms. Initial production of the 55GP begins this quarter, followed later in the year by 55GC.
Even though many of TSMC’s customers have already adopted the 65nm process, the semiconductor maker will allow them, as well as other clients, to test production using its CyberShuttle prototyping program that allows multiple customers and IP suppliers to share the costs of a single mask set and prototype wafers on a pilot run. The 55nm CyberShuttle runs are expected to be offered on a bi-monthly basis starting from the beginning of May this year.
TSMC’s customers who make cost-efficient products, such as ATI, graphics product group of AMD, and Nvidia Corp. are projected by unofficial sources to release first chips made using 55nm process technology in early 2008.