Intel to Describe 32nm Process Technology at International Electron Devices Meeting

Intel to Detail Its 32nm Fabrication Process in Mid-December

by Anton Shilov
10/29/2008 | 08:27 PM

Intel Corp. plans to reveal more details about its 32nm fabrication process at the International Electron Devices Meeting (IEDM) in mid-December, 2008. While the first test chips were build using 32nm process technology more than a year ago, Intel did not provide any details regarding the process itself, possibly because they were subject to change as well as for keeping its rivals without any information.


Apparently, Intel’s 32nm manufacturing process utilizes the company’s second-generation, high-k/metal gate technology, a strained channel, and nine levels of low-k interconnect dielectrics, according to EETimes web-site that cites an Intel’s document available from IEDM’s web-site on request. The process enables the highest drive currents reported to date for 32nm technology: NMOS saturated drive current is 1.55mA/micron while the corresponding PMOS value is 1.21mA/micron.

Intel’s 32nm test chips incorporate logic and memory (static random access memory, SRAM) to house more than 1.9 billion transistors with 4.2Mb² array density. The chip features 0.171 micron² cell size. The process evaluation chip reportedly functioned at 3.80GHz with 1.1V voltage.

Intel plans to commercialize the 32nm process technology in 2009. The node appears to be important for the company as it will enable it to enter the market of ultra low-power x86 microprocessors aimed at handsets, introduce microprocessors with built-in graphics cores and continue to offer higher-performance microprocessors at competitive price-points.

Since the first 32nm SRAM + logic test chips were demonstrated back in September 2007, the intrigue is whether Intel already has working samples of actual microprocessors produced using 32nm fabrication process.