by Anton Shilov
11/06/2008 | 11:55 AM
Taiwan Semiconductor Manufacturing Company (TSMC) will become even more aggressive with rolling-out new fabrication processes. The company plans to make 22nm technology available for customers in 2011, whereas the 15nm fabrication process will go online in 2013. However, since those technologies are pretty expensive to develop, larger wafers may be needed to make them feasible.
“While Moore's Law still applies, the shrinking of technology nodes will have to overcome the barriers of power consumption and costs,” commented company vice president for research and development Jack Sun, reports DigiTimes web-site.
The reduction of manufacturing cost per transistor has been slowing down: costs declined by a compound annual growth rate (CAGR) of 29% between 1993 and 2003, whereas between 2003 and 2018 the CAGR decline will be 26%, according to Mr. Sun. The R&D guru at TSMC claims that once the industry starts producing chips using 32nm process technology, it will be even harder to reduce manufacturing cost per transistor.
One of the ways to reduce production cost per transistor is to implement larger wafers, e.g. 450mm wafers. Since the peak of 300mm wafers production will continue till the year 2014 (2004 - 2014), the rolling out of post-32nm process technologies – such as 15nm in 2013 – may be a rather risky move by TSMC.
Earlier this year there were concerns about lower manufacturing capacities at TSMC for more advanced process technologies.