by Anton Shilov
11/17/2008 | 07:20 AM
Taiwan Semiconductor Manufacturing Co. on Monday announced volume production of the first semiconductor foundry 40nm logic manufacturing process with the successful ramp of its 40nm General Purpose (G) and Low Power (LP) versions.
TSMC’s 40nm G and the 40nm low power (LP) manufacturing processes timetables were formally announced in March this year. The 40G process targets performance-driven applications including central processing units, graphics processing units, chips for game consoles, networking applications, field programmable gate arrays (FPGA), hard disc drives and other devices. The 40LP process targets low-power applications including cellular baseband, application processors, portable consumer and wireless connectivity devices.
TSMC’s 40nmG and 40nm LP processes both passed process qualification, reaching “first wafers out” status as planned and completed product qualification in October when first customer wafers entered production. As with every TSMC process node, the 40G and 40LP processes offer a full range of mixed-signal and RF options, along with embedded memory to support a broad range of analogy/RF-intensive and memory-rich applications.
TSMC's 40G and 40LP processes offer designers up to a 2.35 times raw gate density improvement over the 65nm node. The 40G process is up to 30% faster than TSMC’s 65nm GP process at the same leakage, or up to 70% lower leakage at the same speed. In addition, it provides up to 45% lower active power than the 65GP process. The 40LP process provides up to 46% lower leakage and up to 50% lower active power than TSMC’s 65LP at the same speed. It also features the smallest SRAM cell size, 0.242um2, and macro size in production today.
Multiple customers at 40nm have adopted Reference Flow 9.0, a production-proven design infrastructure that allows designers to take full advantage of 40G and 40LP processes. TSMC’s Reference Flow includes a number of innovative power reduction techniques and tools that allow designers considering 45nm design rules to transparently target their designs to 40nm processes without explicitly dealing with a multitude of scaling factors. Reference Flow also facilitates enhanced timing, statistical design and design for manufacturing (DFM).
The 40nm process is one of the semiconductor industry’s most advanced available for production manufacturing process and is expected to play a key role in the development of next generation products in global consumer electronics, mobile, and computer end markets.
The first customers to adopt TSMC’s 40nm process technologies are graphics processors developers ATI, graphics product group at Advanced Micro Devices, and Nvidia Corp. Altera, a designer of field-programmable gate arrays.
“We view 40nm as an important process node for the cost-effective development of graphics chips and other devices, especially in 2009. This is another example of a long and successful history of AMD and TSMC ramping leading edge processes,” said Rick Bergman, senior vice-president and general manager at ATI, graphics product group at Advanced Micro Devices.
“High-performance GPUs are only continuing to grow in importance for a variety of industries. The advantages that TSMC's 40nm G process provides to designing a GPU will allow us to continue pushing the limits of what's currently possible,” said Debora Shoquist, Nvidia senior vice president of operations.