Intel Describes Peculiarities of 32nm Process Technology

Intel Reveals More Details about 32nm Fabrication Process

by Anton Shilov
02/11/2009 | 05:02 AM

Intel Corp. on Tuesday revealed more details regarding its 32nm process technology that will allow the company to build high-performance and, from some point of view, revolutionary processors. Intel believes that yield rates of the new fabrication process will be very high and combined with reduced leakage and other improvements will further improve Intel’s products and manufacturing efficiencies.

 

The foundation of Intel’s 32nm process technology is the second generation high-k + metal gate transistor. The improvements over the first generation’s high-k + metal gate transistors are many. The equivalent oxide thickness of the high-k dielectric has been reduced from 1.0nm on 45nm to 0.9nm on the 32nm process while gate length as been reduced to 30nm. Transistor gate pitch continues to scale 0.7x every two years - with 32nm providing the tightest gate pitch in the industry.

The company’s 32nm also uses the same basic replacement metal gate process flow as Intel’ 45nm process technology enabling Intel to leverage an existing highly successful process. These improvements are critical for scaling the size of ICs and increasing transistor performance. Intel claims that its 32nm P1268 (for central processing units) and P1269 (for system-on-chip) process technologies with second generation high-k + metal gate transistors enable designers to optimize for both size and performance simultaneously.

The decreased oxide thickness and reduced gate length enables a more 22% transistor performance gain. These transistors provide the highest drive currents and tightest gate pitch reported in the industry. Leakage current can also be optimized for a >5x reduction in leakage over 45nm for NMOS transistors, and over ten times reduction in leakage for PMOS transistors. These improvements combine to enable circuits to be designed that are both smaller and have improved performance/power. 32nm is also 4th generation of strained silicon technology for improved transistor performance – so Intel has had time and opportunity to make vast improvements.

First demonstrated in September of 2007, the 32nm SRAM test chip is a testament to the health of not only the 32nm process, but also of the health of Moore’s law. Moving to 32nm Intel was able to reduce the cell size from the 0.346um² of the 45nm process technology, to 0.171um² for 32nm. Looking back over previous process technology implementations, Intel continues the trend of a 50% reduction in transistor size every two years.

Intel is very proud of the ramp and yields achieved on the 45nm P1266 process. Intel was able to achieve a rapid defect reduction with 45nm technology. According to the company’s the 45nm P1266 process now represents Intel’s highest yielding process ever.

The yield of the 32nm P1268 process is exactly in line with what is required to match or exceed the highly successful ramp of the 45nm process, the company said. Reduction in defect density is currently at the 2 year expected offset from 45nm and Intel fully expects to be at the low defect rates and high yields to be ready for Q4 2009 production.

Intel will be bringing four fabs online over the next two years to transition the processor and system-on-chip lineups to 32nm. D1D in Oregon is currently in operation and D1C in Oregon will come online in Q4 of 2009 to meet demand for 32nm products. In 2010 Intel will add two addition manufacturing facilities to the mix: Fab 32 in Arizona and Fab 11X in New Mexico.