by Anton Shilov
02/24/2010 | 10:40 PM
The problems with 40nm process technology of Taiwan Semiconductor Manufacturing Company have indisputably affected ramp up of graphics processors of both ATI, graphics business unit of Advanced Micro Devices, and Nvidia Corp. very significantly. But it looks like while the vast majority of problems are over, Nvidia Corp., one of TSMC’s largest customers, expects 40nm fabrication process to become problems-free only in the middle of 2010.
“Until December [the output of 40nm wafers] was all about the yields. […] TSMC has made a lot of improvements. They really got a lot of engineering resources engaged and trying to tackle the [40nm process technology] problems. […] Today capacity constraints are equipment related and not so much yield[-related]. […] There is still room for yield improvements. […] We are looking forward the capacity situation [to be solved] somewhere in the middle of the year,” said David White, chief financial officer of Nvidia, at Goldman Sachs Technology Conference.
According to Mr. White, Nvidia started to ramp up production of chips using 40nm fabrication process back in Spring, 2009, however, up until December the yields were unpredictable, which forced Nvidia to sell more 55nm graphics processing units (GPUs) and delay certain product launches.
However, Nvidia expects the problems with 40nm yields to be solved completely in Q2 – Q3 2010, just in time when the company plans to ramp up production of chips based on the new-generation Fermi architecture.
“By the time we begin launching Fermi, which is in volume production today, and which will really become mainstream for us in Q2 – Q3 from a volume standpoint, the yield issues will be past us,” added Mr. White.
It is rather remarkable that it took TSMC so long to polish off the 40nm fabrication process. ATI started to produce its code-named RV740 (Radeon HD 4770) chips back in October, 2008, and while at present ATI has the whole product stack made using 40nm process technology, there are still some yield issues and capacity constraints.