by Anton Shilov
09/16/2010 | 06:02 PM
The PCI special interest group (PCI SIG) is on track to ratify the final version of the PCI Express 3.0 standard in November, 2010. Moreover, according to a media report, Intel Corp. is already gearing up to implement the new high-speed interconnection into its Sandy Bridge generation processors aimed at servers.
The PCI SIG released in mid-August a version 0.9 of the specification of the new PCI Express link with a plethora of new features and massively improved transfer-rate. It is expected by the executives of the standard setting organization that after sixty days (e.g., by November) that the SIG would release a final version of the base spec, reports EETimes web-site.
Earlier this year the organization said that it would begin testing prototypes of products featuring PCI Express 3.0 interconnection in early 2011, therefore, the group is in line with its schedule. Still, according to the report the PCI SIG does not anticipate to complete a specification for testing PCIe 3.0 products until late in 2012 and will only release tools to validate designs and start interoperability workshops in mid-2011.
Manufacturers of 100Gb and 40Gb Ethernet cards, high-end graphics cards, next-generation Infiniband interconnects, ultra high-end solid-state drives will be among the first to implement PCI Express 3.0 into their chips. What is interesting is that Intel's Xeon chips based on Sandy Bridge micro-architecture are also rumoured to feature PCIe 3.0 controller. At this point it is uncertain whether Sandy Bridge chips for multi-processor or dual-processor systems are to get the new type of interconnection to connect to high-speed peripherals and, perhaps, the company's Knights Corner accelerators for high-performance computing applications.
The third-generation incarnation of PCI Express has numerous advantages over existing bus specifications. The PCIe 3.0 will operate at 8GT/s (8.0GHz) speed, will have different electrical models and will move to 128-bit and 130-bit encoding schemes (from 8- and 10-bit schemes). In 2008 Advanced Micro Devices and Hewlett Packard proposed a number of extensions for PCI Express 3.0. One of the extensions is protocol multiplexing, a feature that would allow chips to dynamically switch between seven different protocols in addition to PCIe using the shared set of pins. This would allow creation of chips that would be compatible with PCIe, HyperTransport, QuickPath Interconnect, Ethernet and other buses at the same time. Another extension is called lightweight notification and would allow co-processors or peripheral chips to talk to each other through system memory using a PCIe transaction without interrupting a host processor. For example, an Ethernet switch could respond to commands to encrypt and decrypt specific data packets while a host processor is inactive.