Intel's D1X Fab to Be Ready for 450mm Wafers - Report

Intel's Next-Gen Development Fab Will Be Able to Use 450mm Wafers

by Anton Shilov
10/25/2010 | 10:25 PM

Intel Corp.'s recently announced D1X fab in Hillsboro, Oregon could be the world's first semiconductor manufacturing plant that will be ready to process 450mm wafers, according to analysts. Even though initially it will manufacturer chips using 300mm wafers, going forward Intel will be able to upgrade the equipment to process larger wafers.


''With respect to Intel’s D1X, our checks reveal that it would likely be 450mm ready, but not yet 450mm capable. What does that mean? It means that it would be facilitized with taller ceilings, enhanced clean room capability (capable of pumping out a larger volume and filling it with particle free air), and with pedestals able to support and contain any vibration from bigger and heavier tools. The point being - this does not mean 450mm is ready for prime time, rather Intel is maximizing options," said C.J. Muse, an analyst with Barclays Capital, in a report, according to EETimes web-site.

Intel announced earlier this month that D1X will produce chips using 16nm process technology sometime in 2013, but it is also known that by that timeframe no company in the industry actually plans to use 450mm equipment for manufacturing of actual products. As a result, it is clear that Intel will not even try to wed 450mm wafers with 16nm manufacturing process and it is more likely that the company will only utilize appropriate equipment for chips made using 12nm or 10nm nodes.

In fact, only three companies in the industry are working seriously to start manufacturing of chips on 450mm wafers within the next five years: Intel, Samsung Electronics and Taiwan Semiconductor Manufacturing Company. With only three potential customers, producers of actual equipment are not throwing heavy investments onto development of appropriate equipment.

According to Mr. Muse, there are a number of things ready for 450mm manufacturing:

requirement guidelines; 2. early design; 3. early prototypes; 4. interoperability test bed; 5. mechanical wafer bank; 6. technology intercept node defined; 7. single crystal wafer bank; and 8. equipment performance metrics.

But there are many things that are not: 9. metrology and process equipment development; 10. equipment prototypes; 11. equipment demos; and 12. actual equipment readiness.

''Also, during the same time, the litho industry faces the challenge of making EUV lithography work and overall the semiconductor faces obstacles like a new gate structure, new materials. So, just yet, we believe it is difficult to see 450-mm happening," the analyst said.