PCI Special Interest Group Publishes PCI Express 3.0 Standard

PCI Express 3.0 Standard Finalized at Last

by Anton Shilov
11/18/2010 | 12:00 AM

PCI-SIG, the organization responsible for the widely adopted PCI Express industry-standard input/output (I/O) technology, on Thursday announced the availability of the PCIe 3.0 specification to its members. The PCI Express 3.0 will increase bandwidth and feature-set of the most-widely used I/O bus.

 

“The PCI-SIG remains dedicated to I/O innovation and we are proud to release the PCIe 3.0 specification to our members. The PCIe 3.0 architecture details significant improvements over our two previous PCIe specifications, providing our members with the performance and functionality they need to continue to be innovators in their fields,” said Al Yanes, PCI-SIG chairman and president.

The PCIe 3.0 specification extends the data rate to 8GHz in a manner compatible with the existing PCIe 1.x and 2.x specifications and products that support 2.5GHz and 5GHz signaling. This bit rate represents the most optimum tradeoff between manufacturability, cost, power, complexity and compatibility. Based on this data rate expansion, it is possible for products designed to the PCIe 3.0 architecture to achieve bandwidth near 1GB/s in one direction on a single-lane (x1) configuration and scale to an aggregate approaching 32GB/s on a sixteen-lane (x16) configuration. The new 128b/130b encoding scheme also allows near 100% efficiency, offering a 25% efficiency increase for 8GHz as compared to the 8b/10b efficiency of previous versions, which enables the doubled bandwidth.

PCIe 3.0 technology also maintains backward compatibility with previous PCIe architectures and provides the optimum design point for high-volume platform I/O implementations across a wide range of topologies. Possible topologies include servers, workstations, desktop and mobile personal computers, embedded systems, peripheral devices and more.

“Each new version of the PCIe spec has doubled the bandwidth of the prior generation. The latest group of PCIe architects and designers drove the standard forward while maintaining complete backward compatibility for Gen 1 and Gen 2 devices. Rarely has a standard advanced so non-disruptively through three major evolutionary cycles. The ability to pull this off demonstrates not only the ingenuity of the Gen 3 developers, but also the insight of those who defined the earlier versions in such an extensible manner,” said Nathan Brookwood, research fellow at Insight 64.

This evolutionary specification integrates a number of enhancements to the protocol and software layers of the architecture. These enhancements range in scope from data reuse hints, atomic operations, dynamic power adjustment mechanisms, latency tolerance reporting, loose transaction ordering, I/O page faults, BAR resizing and many more extensions in support of platform energy efficiency, software model flexibility and architectural scalability.