Globalfoundries Tapes Out Its First 20nm Test Chip

Globalfoundries: Customers Can Begin to Evaluate 20nm Designs

by Anton Shilov
08/29/2011 | 09:40 PM

Globalfoundries on Monday said that it had successfully taped out a 20nm test chip using flows from leading EDA vendors Cadence Design Systems, Magma Design Automation, Mentor Graphics Corp., and Synopsys. Globalfoundries said that it is ready for customers to begin evaluating their 20nm designs. The 20nm process adds several advanced manufacturing rules and requires tool providers to collaborate with foundry partners early in the development cycle.

 

“Our model of early collaboration with EDA partners accelerates the overall development cycle, and gives customers accessibility to the inner workings of the process so they can begin targeting their designs to the most advanced manufacturing capabilities with confidence. This success is a major achievement toward market readiness of our newest process, and we will continue to enhance the design enablement support available for it," said Mojy Chian, senior vice president of design enablement at Globalfoundries.

All four EDA companies have demonstrated that their place-and-route (P&R) tools and tech files are capable of supporting the advanced rules associated with the 20nm process. The flows include library preparation steps for double patterning technology, a complex lithography approach that raises new challenges for designers at 20nm and beyond. The 20nm test chip requires double patterning and was implemented with each EDA partner contributing a large placed and routed design. Prior to tape out, each design was thoroughly validated by Globalfoundries and checked against 20nm sign-off verification decks. Early and extensive 20nm collaboration with each EDA partner resulted in all designs being closed rapidly for a successful tapeout.

In addition to demonstrating full support for all of the key steps in a 20nm P&R flow, including double patterning library preparation, placement, clock tree synthesis, hold fixing, routing and post route optimization, Globalfoundries worked with each of the EDA suppliers to include the necessary setup and support for technology and mapping files. The flow will also demonstrate foundry support for extraction, static timing analysis and physical verification. Globalfoundries will make the design, libraries, and complete vendor flow scripts available to customers who wish to evaluate 20nm technology.