by Anton Shilov
12/07/2011 | 09:53 PM
SuVolta, a developer of scalable low-power CMOS technologies, has disclosed details of its deeply depleted channel (DDC) low-power transistor technology, to be presented at IEDM 2011. The technology has potential to reduce power consumption by up to 80% compared to typical designs. Fujitsu Semiconductor and SuVolta have successfully demonstrated ultra-low-voltage 576Kb SRAM blocks with 0.425V voltage, a 50% decrease over standard cells, that use DDC.
"SuVolta’s technology, which we have proven in silicon, has generated a tremendous amount of interest in the semiconductor industry. We are now disclosing the details of our DDC transistor technology so that the industry’s technologists can envision how SuVolta’s technology can lower power consumption, can allow lower supply voltage, and can enable process scaling to sub-20nm," said Dr. Bruce McWilliams, president and chief technology at SuVolta.
SuVolta’s DDC technology – a component of its PowerShrink low-power CMOS platform – provides the industry with a low-power device technology that has been demonstrated to reduce power consumption by 50% without impacting operating speed. When coupled with advanced voltage scaling techniques, the DDC technology can reduce power consumption by 80% or even more.
SuVolta’s DDC transistor reduces threshold voltage (VT) variability and enables continued CMOS scaling. The structure works by forming a deeply depleted channel when a voltage is applied to the gate. In a typical implementation the DDC channel has several regions – an undoped or very lightly doped region, a VT setting offset region and a screening region. Each implementation of SuVolta’s DDC transistor may vary depending on the wafer fabrication facility and specific chip design requirements.
The undoped or very lightly doped region removes dopants from the channel which allows for a deeply depleted channel. This reduces random dopant fluctuation (RDF) thereby enabling VDD scaling and improved mobility for increased effective current.
The VT setting offset region sets the transistor threshold voltage levels, without degrading channel mobility. This region also improves sigma VT over conventional transistors.
The screening region screens the charge and sets the depletion layer depth. It also serves as a body for dynamic VT adjustment through biasing, if desired.
The DDC transistor enables lower power operation by reducing power supply voltage. By controlling VT variation, chips designed using SuVolta DDC technology can achieve a number of benefits, including 30% lower operating voltage with no performance impact, much lower leakage less design “guard banding” and improved yields, according to the company. In addition, DDC transistor allows for the setting of multiple VTs, which is vital for today’s low-power products.