AMD, Globalfoundries, Others Set to Use Fully-Depleted SOI with 14nm, 20nm Chips

AMD, Globalfoundries to Use Fully-Depleted SOI Technology

by Anton Shilov
04/27/2012 | 10:27 PM

Soitec, a leading designer of materials for semiconductors, has announced its fully depleted (FD) product roadmap comprising two products designed for both planar and three-dimensional (FinFET) approaches to building transistors. Industry checks by X-bit show that AMD, Globalfoundries and some other companies are interested in FDSOI for 20nm chips.

 

"Our fully depleted product roadmap addresses the critical needs of the semiconductor industry and solves key challenges facing manufacturers today. Whichever path chip vendors choose to follow – planar or FinFET – Soitec provides solutions that address cost, performance, power-efficiency and time-to-market issues. FD-2D enables immediate and significant performance leaps, while FD-3D makes FinFET a reality for the entire industry at accelerated schedules and reduced risk," said Paul Boudre, chief operating officer of Soitec.

Based on industry checks, X-bit labs believes that Globalfoundries and other partners will use fully-depleted SOI with its 20nm processes and more advanced technologies for making chips, including those designed by Advanced Micro Devices.

Fully-depleted wafers from Soitec, pre-integrate critical characteristics of the transistor within the wafer structure itself. Soitec’s FD wafers offer an early, low-risk migration at the 28nm node down to 10nm and beyond, lowering costs and enabling significant advances in the performance and power efficiency of mobile devices such as smartphones and tablets.

Soitec’s FD-2D product line enables a unique planar approach to fully depleted silicon technology as early as the 28nm node, in which chipmakers can continue to leverage their existing designs and process technologies. FD-2D also enables immediate gains in performance and energy efficiency for mobile and consumer multimedia chips.

The company’s FD-3D product line facilitates the introduction of three-dimensional (FinFET) architectures with reduced time and investment, and drives substantial simplifications in the transistor fabrication process, targeting nodes below 20nm.

Soitec’s proprietary Smart Cut layer transfer technology is said to generate thin layers with high quality and uniformity, bringing the ability to tune starting wafers to successive technology nodes and delivering key advantages as chip manufacturers pursue the best performance, efficiency and manufacturability results.