by Anna Filatova
02/05/2002 | 10:37 PM
As I have predicted (see this news story), on February 4 Intel disclosed some details about its Itanium CPU based on the new McKinley core. Have a look at the following chart:
It shows almost all the noticeable differences between the McKinley and Merced cores. What are they?
| Parameter | Merced | McKinley |
|---|---|---|
| Initial core clock | 800MHz | 1GHz |
| System bus frequency | 266MHz | 400MHz |
| System bus width | 64bit | 128bit |
| System bus maximum theoretical bandwidth | 2.1GB/sec | 6.4GB/sec |
| Processor | 64bit | |
| L1 cache | 32KB on-die | |
| L2 cache | 96KB on-die | 256KB on-die |
| L3 cache | max. 4MB (off-die) | max. 3GB (on-die) |
| Pipeline stages | 10 | 8 |
| Resulting ports | 9 | 11 |
| Number of registries | 328 | |
| Execution units | 4 integer units (3 branch), 2 FP, 2 SIMD 2 load and 2 store | 6 integer units (3 branch), 2 FP, 2 SIMD, 1 load and 2 store |
| Instructions per clock (max.) | 6 | |
In addition, they claim that McKinley core will comprise... 221 million transistors! Well, now it becomes clear which processors will be the ones to break the 1 billion bar in 2007 (see this news story).
According to the official sources, Itanium (McKinley) should be produced in mass quantities in the middle of this year. the fastest Itanium model on the new 0.18micron McKinley core, 1GHz clock frequency and 3MB L3 cache will make $4220 per piece in 1,000-unit quantities (this info is unofficial so far).