The Open NAND Flash Interface (ONFI) Working Group, the organization dedicated to simplifying integration of NAND Flash memory into consumer electronics (CE) devices, computing platforms and industrial systems, today announced the availability of the ONFI 2.1 specification.
The chip-level standard interface is the latest in the line of succession of ONFI working group’s previous standards: ONFI 1.0 and ONFI 2.0. Like the previous installments, ONFI 2.1 offers simplified flash controller design, but pushes performance levels to a new range – 166MB/s to 200 MB/s. Looking to the future, ONFI also announced that it has started a process to define the next specification, ONFI 3.0 that will reach speeds of up to 400 MB/s.
ONFI 2.1 answers the call for increased overall NAND performance at a time when faster speeds are a critical design factor for flash memory-based devices such as solid state drives (SSDs), especially as the interfaces those SSDs connect to offer faster data rates with Serial ATA 6 Gb/s, USB 3.0, and PCI Express 2.0.
Additionally, after recognizing the influx in consumer demand for low-cost consumer products such as netbooks, as well as the need to implement low-cost, yet high-performance flash memory to support these devices, ONFI 2.1 has introduced a Small Data Move command to the specification. The Small Data Move command eliminates the costly and substantial internal memory requirements once necessary for proper error correction in these low-cost memory architectures.
“ONFI provides a strong platform for next generation embedded and consumer electronics devices. Creating system-level standards for memory is fundamental for the evolution of the Flash NAND industry, and Numonyx is proud to contribute to this effort. Building on the standardized command set and pin-out, provided by the ONFI 1.0 specification, the ONFI 2.1 release helps set the foundation for next-generation high-speed applications,” said Mark Leinwander, system architecture manager at Numonyx.
The ONFI Working Group has worked productively with The Joint Electron Device Engineering Councils (JEDEC) over the past six months as part of a joint task group focused on future NAND standardization efforts. Any ONFI or JEDEC member is welcome to participate in these efforts. The ONFI 2.1 specification has been provided to the joint task group as material for continuing collaboration.
Additional features and capabilities introduced in the ONFI 2.1 specification include:
- ONFI 2.1 standard is compatible with ONFI 2.0, ONFI 1.0, and the legacy NAND interface.
- More Performance for Interleaved Reads. ONFI 2.1 has added support for interleaved reads, enabling deeper pipelining of reads particularly in MLC architecture where the array time can be longer.
- Improved ECC Communication. As the raw bit error of NAND increases, the amount of ECC applied increases. ONFI 2.1 allows NAND devices to communicate multiple sets of ECC parameters together through extended ECC Information.
- Enhanced Power Management. ONFI 2.1 allows the host to stop the clock during writes to the NAND, allowing savings of up to 10s of milliwatts.
- New Change Row Address Command. In MMC and SD applications, there are commands that allow the host to write indefinitely. When the host stops writing, it may be in the middle of a page, putting stress on the NAND. The Change Row Address command changes the location the page is being written to, avoiding writing an incomplete page to the final location and relieving stress on the NAND.