Modern graphics processors are so complex that no company can avoid mistakes when developing new chips. A lot of capabilities, patterns and other blocks of GPUs are eventually cured by software and drivers, whereas those bugs in hardware design that cannot be treated easily are simply ignored and certain capabilities are disabled, as it always costs too lot of money and time to address an issue when you have to create chips that consist millions of transistors every 6 to 9 month. Therefore, never expect a hardware bug to be corrected before the next chip is out. I can remember that the TNT-series of graphics chips were not able to do trilinear filtering, while the GeForce256, GeForce2 and GeForce3 had a bug with S3TC decompression, S3’s Savage2000 featured a T&L that never worked, ATI’s Rage128 Pro supported anisotropic filtering that was disabled in drivers. This week it was revealed that the latest NVIDIA’s GeForce FX graphics processor features only 4 rendering pipelines, but not 8, as the Santa Clara, California-based VPU developer claims everywhere on its web-site.

Our colleagues over at The Inquirer web-site received a couple of days ago confirmation from an NVIDIA’s representative that the GeForce FX VPU has 4 rendering pipelines with 2 TMUs per each pipe. The formerly known as code-named NV30 can therefore do 8 textures per clock only in multitexturing. An NVIDIA’s fellow adder that there are certain cases where the GeForce FX can work with 8 textures:

• z-rendering;
• stencil operations;
• texture operations;
• shader operations.

Color + Z rendering is done at 4 pixels per clock.

I wonder if there are any other peculiarities in the actual architecture of the GeForce FX VPU that NVIDIA decided to keep confidential. And what about the architecture of the GeForce FX derivatives?