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ATI’s Next-Gen R520 VPU to be Announced in June – ATI’s Top Partner Says.

Category: Video

by Anton Shilov

[ 04/03/2005 | 10:24 PM ]

A spokesperson for graphics cards maker Sapphire Technologies revealed some peculiarities in regards the launch of ATI Technologies’ new visual processing unit known under R520 code-name. According to the official, the chip will be introduced early this Summer.

ATI’s R520 to be Launched in June

“As per the current plans, we expect ATI to announce their new GPU(s) in June,” said Dan Foster, PR and marketing manager for EMEA region in an interview with t-break web-site.

The web-site claims that according to Sapphire, RADEON X850 XT flavour with 512MB of local buffer is unlikely to be a commercial products “because of the low yields,” nevertheless, the world “will see another ATI GPU-based 512MB card shortly.”

Late last year analyst firm Credit Suisse First Boston said ATI’s R520 chip had been taped out and ATI had completed wafer test on 90nm nodes from TSMC. The CSFB believed ATI would be on-track to introduce the visual processing unit (VPU) in Spring, 2005.

ATI Technologies did not comment on the news-story.

Specifications Unclear

Not much is known about the architecture and capabilities of the code-named R520 product that was initially referred as the R500. What is clear now is that the new graphics chip will sport Shader Model 3.0 – pixel shaders 3.0 and vertex shaders 3.0 – bringing additional programming capabilities to ATI’s future graphics processors as well as some other innovations.

Specifications of ATI’s code-named R520 VPU are unclear at this time. Some sources suggest that the chip may have up to 32 pixel pipelines and up to 350 million transistors, which makes the processor extremely complex. However, given that a new fabrication process is to be used for the manufacturing of R520, it is unlikely that the visual processing unit will be tremendously large in terms of transistor count and complex in terms of the number of pipelines. Fabless semiconductor designers tend to balance complexity of their chips for new fabrication processes. For instance, since 2002, ATI has not launched manufacturing of high-end graphics chips using a new process technology unless the technology was tested on mainstream chips. Still, even on relatively new manufacturing processes, ATI has set pretty high clock-speeds for its VPUs.

R520 – Shader Model 3.0 VPU

ATI’s R5xx architecture will not resemble that of the previous generation products and NVIDIA’s GeForce 6 architecture known as NV4x; particularly ATI will implement efficient flow-control, a crucial feature for pixel shaders 3.0, that will not bring speed penalty it does on existing SM3.0 hardware, according to sources. The future of the graphics hardware lies in higher number of ALUs ops per texture ops, unified pixel and vertex shaders as well as some other requirements of Microsoft Windows Longhorn operating system, such as virtualization and context switches. While ATI agrees on the long-term goals for its roadmap, it does not name feature-set of actual products and says all the architectural changes will be implemented gradually, not at once.

ATI Technologies’ developer relations manager Richard Huddy said during a conference in November, 2004, that the company’s future visual processing units would feature unified pixel and shader processing. While he declined to elaborate on the timeframes for such chips, he said unified pixel and vertex data processing was a required capability for Windows Graphics Foundation 2.0 that comes out together with Microsoft’s next-generation operating system called Windows Longhorn. On of the benefits the unified approach brings is ability to dynamically allocate chip resources depending on the demand for pixel and vertex processing, Mr. Huddy said. Another one is simplified software development.

Some sources claim that the R500 is a code-name of ATI’s graphics processor that will be submitted for Microsoft’s next Xbox console. The shader core of the R500 was reported to have 48 Arithmetic Logic Units (ALUs) that can execute 64 simultaneous threads on groups of 64 vertices or pixels. ALUs are automatically and dynamically assigned to either pixel or vertex processing depending on load. The ALUs can each perform one vector and one scalar operation per clock cycle, for a total of 96 shader operations per clock cycle. Texture loads can be done in parallel to ALU operations. At peak performance, the GPU can issue 48 billion shader operations per second, it was indicated.

The R520 is also expected to feature advanced memory interface, presumably supporting GDDR4 memory.