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RADEON 9500: Next Week. SiS Xabre 600: This Quarter

by Anton Shilov
10/07/2002 | 04:25 PM

Not only NVIDIA will unveil its highly-anticipated NV30 graphics processor this quarter. Both ATI and SiS also plan to launch a number of additions to their product families. Originally, some fans of Matrox told that the second Canada based graphics cards’ developer may also launch the improved version of its Parhelia graphics processor with full DirectX 9.0 support and manufactured using thinner 0.13 micron technology this year. It now can be hardly believed that Matrox Graphics will really be able to introduce something new made using more advanced process in 2002, since UMC has a number of problems with 0.13 micron technology (see this news-story) at the moment.

According to preliminary details whispered by our sources from ATI, the company plans to reveal the RADEON 9500 and the RADEON 9500 PRO early next week. Both RADEON 9500 and 9500 PRO are derivatives from the RADEON 9700 VPU. Both support AGP 8x, DirectX 9.0, provide four geometry engines, dual 400MHz RAMDACs, HyperZ-III, TrueForm 2.0 and so on. In order to lower the costs of their mainstream solutions, ATI decided to use 128-bit memory bus for the RADEON 9500 and RADEON 9500 PRO based graphics cards. All the RADEON 9500 powered products will be clocked at 275/550MHz for core/memory. The difference between the PRO and “non PRO” versions is the number of rendering pipelines: eight for the former and four for the latter. For more information and details see this news-story. ATI has not yet set the date for the RADEON 9000 series graphics chip with AGP 8x support to be rolled-out. However, unofficial sources think that the company will announce it before the year end.<%BANNER[article]%>

Also SiS will offer us a new product this quarter. In fact, it is going to be another Xabre GPU that will have the same features as all of the family, but will be clocked at 275MHz for core and 275MHz for memory. SiS Xabre 600 features four rendering pipelines with two TMUs per each, supports pixel shaders and emulates vertex shaders using the CPU of the system.

NVIDIA code-named NV30 will be announced at Comdex Fall on the 18th of November. The VPU features 8 rendering pipelines with 2 TMUs on each one, beyond DirectX 9 shaders support, 256-bit DDR SDRAM memory, AGP 8x and a lot more technical innovations, about some of them you can read in this news-story that was issued in July.

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