Articles: Memory

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DDR2: Theoretical Basics

To understand the advantages and shortcomings of DDR2 SDRAM in comparison to DDR SDRAM we should learn some basic facts about its architecture. First of all, you should be aware that DDR2 memory is fundamentally similar to DDR SDRAM. Still, while DDR SDRAM can transfer data across the bus two times per clock, DDR2 SDRAM can perform four transfers per clock. DDR2 uses the same memory cells, but doubles the bandwidth by using the multiplexing technique.

The DDR2 memory cell is still clocked at the same frequency as DDR SDRAM and SDRAM cells, but the frequency of the input/output buffers is higher with DDR2 SDRAM. The bus that connects the memory cells with the buffers is twice wider compared to DDR. Thus, the I/O buffers perform multiplexing: the data is coming in from the memory cells along a wide bus and is going out of the buffers on a bus of the same width as in DDR SDRAM, but of a twice bigger frequency. This allows to increase the memory bandwidth without increasing the operational frequency of the memory cells (the DDR2-533 cell works at the same frequency as a DDR266 SDRAM or a PC133 SDRAM cell, and the transition from DDR SDRAM to DDR2 SDRAM resembles much the transition from SDR SDRAM to DDR SDRAM). Still, this simple method of increasing the memory bandwidth has its downsides, too. The main disadvantage is high latency. The memory latency does not depend on the frequency of the I/O buffers or on the width of the bus the data are coming in from the memory cells. The main factor affecting the latency is the latency of the memory cells themselves. The latency of DDR2-533 is comparable to that of DDR266 or PC133 SDRAM and is evidently worse compared to the latency of DDR400 and higher. Thus, DDR2 SDRAM has a higher bandwidth but worse latency than DDR SDRAM, and this is why DDR2-based systems would lose to their DDR-based counterparts in real applications (there are many applications that are sensitive not only to the speed at which data are being transferred to them, but also to the time it takes to access those data).

Besides the higher frequency of the I/O buffers and the use of a twice higher multiplex coefficient, DDR2 has some other unique features, of relatively less importance. The following table lists them:





200, 266, 333, 400 MHz

400, 533, (667, 800) MHz

Chips Packaging




2.5 V

1.8 V


64 Mbit – 1 Gbit

256 Mbit – 4 Gbit

Internal Banks


4 and 8

Prefetch (MIN Write Burst)



CAS Latency (CL)

2, 2.5, 3

3, 4, 5

Additive Latency (AL)

No support

0, 1, 2, 3, 4

Read Latency



Write Latency


Read latency - 1

Input Calibration

No support

Off-Chip Driver (OCD) Calibration

Data Strobes

Bidirectional Strobe (single ended)

Bidirectional Strobe (single ended or differential) with RDQS

On-Chip Bus Termination



Burst Lengths

2, 4, 8

4, 8

In fact, we can only emphasize the Additive Latency mechanism and the on-chip bus termination. Additive Latency increases the efficiency of data transfers somewhat as it solves the problem that sometimes occurs with DDR SDRAM when a command to read an initialized memory bank and a command to initialize the next bank cannot be issued simultaneously. This innovation brings just a minor performance gain in reality, though.

On-die termination means that the resistors on the end of the bus (to suppress the signal, rather than to let it echo back into the bus) are located on the chip rather than on the mainboard as before. This improves the termination proper and decreases the cost of mainboards as it’s not necessary to put resistors around the DIMM slots.

As said explicitly in the specification, DDR2 SDRAM chips have FBGA packaging. This type of packaging allows for better heat takeoff as well as minimal electromagnetic interference between the chips. Besides the different packaging (DDR SDRAM chips were usually TSOP-packaged), DDR2 SDRAM chips have a smaller power voltage and thus a smaller heat dissipation (about 30 percent less). By the way, this permits to create DDR2 chips of higher capacities and frequencies than it was possible with DDR SDRAM.

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